Integrated chip package structure using metal substrate and method of manufacturing the same

ABSTRACT

An integrated chip package structure and method of manufacturing the same is by adhering dies on a metal substrate and forming a thin-film circuit layer on top of the dies and the metal substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the priority benefit of Taiwanapplication serial no. 90133194, filed Dec. 31, 2001.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to an integrated chip packagestructure and method of manufacture the same. More particularly, thepresent invention relates to an integrated chip package structure andmethod of manufacture the same using metal substrate.

[0004] 2. Description of Related Art

[0005] In the recent years, the development of advanced technology is onthe cutting edge. As a result, high-technology electronics manufacturingindustries launch more feature-packed and humanized electronic products.These new products that hit the showroom are lighter, thinner, andsmaller in design. In the manufacturing of these electronic products,the key device has to be the integrated circuit (IC) chip inside anyelectronic product.

[0006] The operability, performance, and life of an IC chip are greatlyaffected by its circuit design, wafer manufacturing, and chip packaging.For this present invention, the focus will be on chip packagingtechnique. Since the features and speed of IC chips are increasingrapidly, the need for increasing the conductivity of the circuitry isnecessary so that the signal delay and attenuation of the dies to theexternal circuitry are reduced. A chip package that allows good thermaldissipation and protection of the IC chips with a small overalldimension of the package is also necessary for higher performance chips.These are the goals to be achieved in chip packaging.

[0007] There are a vast variety of existing chip package techniques suchas ball grid array (BGA), wire bonding, flip chip, etc . . . formounting a die on a substrate via the bonding points on both the die andthe substrate. The inner traces helps to fan out the bonding points onthe bottom of the substrate. The solder balls are separately planted onthe bonding points for acting as an interface for the die toelectrically connect to the external circuitry. Similarly, pin gridarray (PGA) is very much like BGA, which replaces the balls with pins onthe substrate and PGA also acts an interface for the die to electricallyconnect to the external circuitry.

[0008] Both BGA and PGA packages require wiring or flip chip formounting the die on the substrate. The inner traces in the substrate fanout the bonding points on the substrate, and electrical connection tothe external circuitry is carried out by the solder balls or pins on thebonding points. As a result, this method fails to reduce the distance ofthe signal transmission path but in fact increase the signal pathdistance. This will increase signal delay and attenuation and decreasethe performance of the chip.

[0009] Wafer level chip scale package (WLCSP) has an advantage of beingable to print the redistribution circuit directly on the die by usingthe peripheral area of the die as the bonding points. It is achieved byredistributing an area array on the surface of the die, which can fullyutilize the entire area of the die. The bonding points are located onthe redistribution circuit by forming flip chip bumps so the bottom sideof the die connects directly to the printed circuit board (PCB) withmicro-spaced bonding points.

[0010] Although WLCSP can greatly reduce the signal path distance, it isstill very difficult to accommodate all the bonding points on the diesurface as the integration of die and internal devices gets higher. Thepin count on the die increases as integration gets higher so theredistribution of pins in an area array is difficult to achieve. Even ifthe redistribution of pins is successful, the distance between pins willbe too small to meet the pitch of a printed circuit board (PCB).

SUMMARY OF THE INVENTION

[0011] Therefore the present invention provides an integrated chippackage structure and method of manufacturing the same that uses theoriginal bonding points of the die and connect them to an externalcircuitry of a thin-film circuit layer to achieve redistribution. Thespacing between the redistributed bonding points matches the pitch of aPCB.

[0012] In order to achieve the above object, the present inventionpresents a chip package structure and method of manufacturing the sameby adhering the backside of a die on a metal substrate, wherein theactive surface of the die has a plurality of metal pads. A thin-filmcircuit layer is formed on top of the die and the metal substrate, wherethe thin-film circuit layer has an external circuitry that iselectrically connected to the metal pads of the die. The externalcircuitry extends to a region that is outside the active area of thedies and has a plurality of bonding pads located on the surface layer ofthe thin-film layer circuit. The active surface of the die has aninternal circuitry and a plurality of active devices, where signals canbe transmitted from one active device to the external circuitry via theinternal circuitry, then from the external circuitry back to anotheractive device via the internal circuitry. Furthermore, the metalsubstrate has at least one inwardly protruded area so the backside ofthe die can be adhered inside the inwardly protruded area and exposingthe active surface of the die. Finally, the present package structureallows multiple dies with same or different functions to be packagedinto one integrated chip package and permits electrically connectionbetween the dies by the external circuitry.

[0013] It is to be understood that both the foregoing generaldescription and the following detailed description are exemplary, andare intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention. In the drawings,

[0015]FIGS. 1A to 1I are schematic diagrams showing the sectional viewof the structure of the first embodiment of the present invention.

[0016]FIGS. 2A to 2C are schematic diagrams showing the sectional viewof the structure of the second embodiment of the present invention.

[0017]FIGS. 3A to 3C are schematic diagrams showing the sectional viewof the structure of the third embodiment of the present invention.

[0018]FIGS. 4A to 41 are schematic diagrams showing the sectional viewof the structure of the forth embodiment of the present invention.

[0019]FIGS. 5A to 5E are schematic diagrams showing the sectional viewof the structure of the fifth embodiment of the present invention.

[0020]FIG. 6 is a schematic diagram showing the sectional view of thechip package structure of a preferred embodiment of the presentinvention with one die.

[0021]FIG. 7 is a schematic diagram showing the sectional view of thechip package structure of a preferred embodiment of the presentinvention with a plurality of dies.

[0022]FIG. 8 is a magnified diagram showing the sectional view of thechip package structure of a preferred embodiment of the presentinvention.

[0023]FIGS. 9A, 9B are schematic diagrams of the top and side viewrespectively of the patterned wiring layer of the thin-film circuitlayer with a passive device.

[0024]FIG. 10A is a schematic diagram of the formation of a passivedevice by a single layer of patterned wiring layer of the thin-filmcircuit layer.

[0025]FIG. 10B is a schematic diagram of the formation of a passivedevice by a double layer of patterned wiring layer of the thin-filmcircuit layer.

[0026]FIG. 11A is a schematic diagram of the formation of a passivedevice by a single layer of patterned wiring layer of the thin-filmcircuit layer.

[0027]FIG. 11B is a schematic diagram of the formation of a passivedevice by a double layer of patterned wiring layer of the thin-filmcircuit layer.

[0028]FIG. 11C is a schematic diagram of the formation of a passivedevice by a double layer of patterned wiring layer of the thin-filmcircuit layer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] Please refer to FIG. 1A, a metal substrate 110 with a surface 112and a plurality of dies 120 are provided. Wherein the material of metalsubstrate includes pure metal or metal alloy for example copper (Cu),aluminum alloy, or the like. Dies 120 have an active surface 122 and abackside 124 is also provided, where the active devices are formed onactive surface 122 of the dies 120. Furthermore, dies 120 have aplurality of metal pads 126 located on active surface 122 of dies 120acting as the output terminal of dies 120 to transmit signals to theexternal circuitry. Backside 124 of dies 120 is adhered to surface 112of metal substrate 110 by a conductive paste or adhesive tape.Therefore, active surface 122 of dies 120 is facing upwards alongsurface 112 of metal substrate 110.

[0030] Please refer to FIG. 1B, when adhering die 120 to metal substrate110, a filling layer 130 can be formed on top of surface 112 of metalsubstrate 100 surrounding the peripheral of dies 120 to fill the gapbetween dies 120. The height of filling layer 130 should beapproximately equal to the height of active surface 122 of dies 120. Thematerial of filling layer 130 can be epoxy, polymer, or the like. Aftercuring of filling layer 130, a grinding or etching process is applied toplanarize filling layer 130 so the top face of filling layer 130 isplanar with active surface 122 of dies 120.

[0031] Please refer to FIG. 1C, after the formation of filling layer 130on metal substrate 110, a dielectric layer 142 is formed on top offilling layer 130 and active surface 122 of dies 120. Dielectric layer142 is patterned according to metal pads 126 on dies 120 to formthru-holes 142 a. The material of dielectric layer 142 can be poly-Imide(PI), benzocyclobutene (BCB), porous dielectric material, stress buffermaterial, or the like. Patternization of dielectric layer 142 can beperformed by photo via, laser ablation, plasma etching, or the like.

[0032] Please continue to refer to FIG. 1C, filling layer 130 is used tosupport dielectric layer 142 so dielectric layer 142 can be formedplanarized on top of metal substrate 110 and dies 120 without an unevensurface. As a result, after dielectric layer 142 is formed on surface112 of metal substrate 110 and active surface 122 of dies 120,dielectric layer 142 also fills the peripheral of dies 120, meaning thegap between dies 120. Therefore the bottom structure of dielectric layer142 can replace the structure of filling layer 130 covering entirelysurface 112 of metal substrate 110 and surrounding dies 120. The methodof forming dielectric layer 142 includes first forming a layer ofdielectric layer 142 entirely over dies 120 and metal substrate 110,then after curing, a grinding or etching process is performed toplanarize dielectric layer 142. .

[0033] Please refer to FIG. 1D, after forming dielectric layer 142 andpatterning dielectric layer 142 to form thru-holes 142 a, a layer ofpatterned wiring layer 144 is formed by photolithography and sputtering,electroplating, or electro-less plating. Wherein part of the conductivematerial from patterned wiring layer 144 will be injected intothru-holes 142 a to form vias 142 b, copper (Cu) is used as the materialfor patterned wiring layer 144. Moreover, thru-holes 142 a can bepre-filled with a conductive material such as a conductive glue to formvias 142 b. Therefore no matter if the thru-holes are filled with theconductive material from patterned wiring layer 144 or pre-filled with aconductive material, patterned wiring layer 144 is electricallyconnected to metal pads 126 of dies 120. It is to be noted that part ofpatterned wiring layer 144 extends to a region outside active surface122 of dies 120. Dielectric layer 142 and patterned wiring layer 144form a thin-film circuit layer 140.

[0034] Please refer to FIG. 1E, after the formation of patterned wiringlayer 144, another dielectric layer 146 can be formed similarly todielectric layer 142 on top of dielectric layer 142 and patterned wiringlayer 144. Dielectric layer 146 is also patterned to form thru-holes 146a, whereas thru-holes 146 a correspond to bonding pads 144 a ofpatterned wiring layer 144.

[0035] Please refer to FIG. 1F, after the formation and patternizationof dielectric layer 146 to form thru-holes 146 a, a patterned wiringlayer 148 can be formed on dielectric layer 146 in a similar way aspatterned wiring layer 144. Wherein part of the conductive material frompatterned wiring layer 148 will be injected into thru-hole 146 a forminga via 146 b. By the same token, patterned wiring layer 148 iselectrically connected to patterned wiring layer 144 by vias 146 b, andfurther electrically connected to metal pads 126 of die 120 by vias 142b of thru-hole 142 a. Therefore, thin-film circuit layer 140 furthercomprises dielectric layer 146, a plurality of vias 146 b, and patternedwiring layer 148.

[0036] Please continue to refer to FIG. 1F, in order to redistribute allmetal pads 126 of dies 120 on metal substrate 110, the number ofpatterned wiring layers (144, 148 . . . ) and dielectric layers (142,146 . . . ) for electrical insulation may be increased. All patternedwiring layers (144, 148 . . . ) are electrically connected by vias (146b . . . ) of thru-holes (146 a . . . ). However if only the firstpatterned wiring layer 144 is required to entirely redistribute metalpads 126 of dies 120 on metal substrate 110, extra dielectric layers(146 . . . ) and patterned wiring layers (148 . . . ) will no longer berequired in the structure. In other words, thin-film circuit layer 140comprises at least one dielectric layer 142, one patterned wiring layer144, and a plurality of vias 142 b. Wherein patterned wiring layer (144,148 . . . ) and vias (142 b, 146 b . . . ) of thin-film circuit layer140 form an external circuitry of thin-film circuit layer 140.

[0037] Please refer to FIG. 1G, after the formation of patterned wiringlayer 148, a patterned passivation layer 150 is formed on top ofdielectric layer 146 and patterned wiring layer 148. Patternedpassivation layer 150 is used to protect patterned wiring layer 148 andexpose the plurality of bonding pads 148 a of patterned wiring layer148, whereas some of bonding pads 148 a are in a region outside ofactive surface 122 of dies 120. As previously mentioned, theredistribution of metal pads 126 on metal substrate 110 requiresmultiple layers of patterned wiring layers (144, 148 . . . ) and apatterned passivation layer 150 formed on the very top, which isfurthest away from metal substrate 110. However, if only patternedwiring layer 144 is required to redistribute metal pads 126 of dies 120on metal substrate 110, patterned passivation layer 150 will be formeddirectly on patterned wiring layer 144. The material of passivationlayer 150 can be anti-solder insulating coating or other insulatingmaterial.

[0038] Please refer to FIG. 1H, after the formation of patternedpassivation layer 150, a bonding point 160 can be placed on bonding pads148 a serving as an interface for electrically connecting die 120 to theexternal circuitry. Wherein bonding point 160 illustrated in FIG. 1H isa ball but it is not limited to any formation, which might include abump, pin, or the like. Ball connector maybe solder ball, and bumpconnector maybe solder bump, gold bump, or the like.

[0039] Please refer to FIG. 1I, after the formation of bonding points160 on bonding pads 148 a, a singularization process of packaged die 120by mechanical or laser cutting is performed along the dotted line asindicated in the diagram. Afterwards, the chip package structure of thedie is completed.

[0040] According to the above, the first embodiment of the presentinvention is a chip package structure with a metal substrate and aplurality dies on it. The external circuitry of the thin-film circuitlayer allows the metal pads of the die to fan out. By forming bondingpads corresponding to the metal pads of the dies such as solders balls,bumps, or pins as the signal input terminals, the distance of the signalpath is effectively decreased. As a result, signal delay and attenuationis reduced to increase performance of the die.

[0041] Furthermore, the dies are directly touching the metal substrate,which helps the chips dissipate the high heat generated during operationbecause of the high heat conductivity of metal. Performance of the chipwill thereby be increased. Moreover the fabrication technique on metalsubstrate is already well known in the art and the cost of metal is low,the present invention can effectively lower the cost of chip packagingand also increase performance of the chip by providing a medium for heatdissipation.

[0042] The second embodiment of the present invention differs from thefirst embodiment by having inwardly protruded areas in the metalsubstrate. This area is for placement of the die with the backside ofthe die adhered to the bottom of the area so the overall thickness ofthe chip package structure is reduced. FIGS. 2A to 2C are schematicdiagrams of the sectional view of the second embodiment illustrating thefabrication of the structure.

[0043] Please refer to FIG. 2A, a metal substrate 210 with a surface 212is provided. In FIG. 2B, multiple inwardly protruded areas 214 areformed on metal substrate 210 by machining such as milling. The depth ofeach inwardly protruded area 214 is approximately equal to the thicknessof die 220, therefore the outline and depth of inwardly protruded areas214 will be the same as dies 220 in FIG. 2C. In FIG. 2C, backside 224 ofdies 220 is adhered to the bottom of inwardly protruded areas 214 sodies 220 are inlayed in inwardly protruded areas 214. Active surface 222of die 220 is exposed along surface 212 or ceramic substrate 210.

[0044] The structure of the second embodiment of the present inventionafter FIG. 2C will follow FIGS. 1C to 1I from the first embodiment ofthe present invention, therefore it will not be repeated.

[0045] The second embodiment of the present invention is a metalsubstrate with a plurality of inwardly protruded areas for inlaying diesby adhering the backside of the dies to the bottom of the inwardlyprotruded areas and exposing the active surface of the dies. A thin-filmcircuit layer is formed on top of the dies and the metal substrate tofan out the metal pads of the dies by using the external circuitry ofthe thin-film circuit layer. Due to the inlay of the dies in the metalsubstrate, thinning of the thickness of the chip package structure iseffectively achieved and the surface of the metal substrate providesenough planarity and support for the formation of the thin-film circuitlayer.

[0046] The third embodiment of the present invention differs from thesecond embodiment of the present invention by using an alloy metalsubstrate. FIGS. 3A to 3C are schematic diagrams of the sectional viewof the third embodiment illustrating the fabrication of the structure.

[0047] Please refer to FIG. 3A, a metal substrate 310 is constructedwith a first metal layer 310 a and a second metal layer 310 b. A surface312 of metal substrate 310 is the face of second metal layer 310 b thatis further away from first metal layer 310 a. A plurality of openings314 a is formed on first metal layer 310 a by punching and the thicknessof first metal layer 310 a is approximately equal to that of dies 320 sothe depth of openings 314 a is approximately equal to the thickness ofdies 320.

[0048] In FIG. 3B, first metal layer 310 a is placed overlapping secondmetal layer 310 b so openings 314 a of first metal layer 310 a forminwardly protruded areas 314 on the surface of second metal layer 310 b.Following in FIG. 3C, backside 324 of die 320 is adhered to the bottomof inwardly protruded areas 314 so dies 320 are inlayed in metalsubstrate 310 with active surface 322 of die 320 exposed along surface312 of metal substrate 310.

[0049] The structure of the third embodiment of the present inventionafter FIG. 3C will follow FIGS. 1C to 1I from the first embodiment ofthe present invention, therefore it will not be repeated.

[0050] The third embodiment of the present invention is a metalsubstrate consists of a first metal layer with a plurality of openingsand a second metal layer. The openings on the first metal layer willform inwardly protruded areas on the metal substrate. The backside ofthe die adheres to the bottom of the inwardly protruded areas so thedies are inlayed in the inwardly protruded areas exposing the activesurface of the dies. This metal substrate can efficiently dissipate heatfrom the dies to the outside because the bottom of the inwardlyprotruded area is the surface of the heat conducting material. Thesurface of the first metal layer provides enough planarity and supportfor the formation of the thin-film circuit layer. The metal substrateboard of the third embodiment of the present invention is fabricated byoverlapping a first metal layer with openings formed by punching and asecond metal layer. The cost of fabricating the metal substrate is lowbecause punching is low-cost and efficient, which will lower the cost ofchip packaging.

[0051] The fourth embodiment of the present invention is slightlydifferent from the first three embodiments. FIGS. 4A to 4E are schematicdiagrams of the sectional view of the fourth embodiment illustrating thefabrication of the structure.

[0052] Please refer to FIG. 4A, a metal substrate 410 with a firstsurface 412 and an insulating layer 414 of material such as metalnitride or metal oxide formed on top of first surface 412 of metalsubstrate 410. The thickness of insulating layer 414 is about 2 micronsto 200 microns, usually 20 microns. Following, a plurality of dies 420having an active surface 422, a backside 424, and a plurality of metalpads 426 located on active surface 422 is provided. The fourthembodiment of the present invention differs from the third embodiment ofthe present invention by placing active surface 422 of die 420 downwardsfacing first surface 412 of metal substrate 410.

[0053] Please refer to FIG. 4B, a filling layer 430 is formed on top ofinsulating layer 414 after active surface 422 of die 420 is adhered tofirst surface 412 of metal substrate 410. Filling layer 430 coversentirely first surface 412 of metal substrate 410 and surrounds dies420. The material of filling layer 430 maybe an oxide, epoxy, or thelike.

[0054] Please refer to FIG. 4C, after the formation of filling layer430, a planarization process such as chemical mechanical polishing (CMP)is performed to planarize filling layer 430 and backside of die 420.Although the thickness of the active devices and wiring (not shown) onactive surface 422 of die 420 is much less than that of die 420, thethickness of die 420 should not be too small because cracks or damage tothe die will occur during machine handling. However the presentinvention directly adheres active surface 422 of die 420 on firstsurface 412 of metal substrate 410 without further machine handling (forexample vacuum suction). Afterwards a CMP process is performed onbackside 424 of dies 420 to reduce the thickness of dies 420. As aresult, dies 420 are ground to a very small thickness allowing the finalchip package structure to be much thinner.

[0055] Please refer to FIG. 4D, after the planarization of filling layer430 and dies 420, a second metal substrate 440 with a second surface 442is adhered to filling layer 430 and dies 420 creating a sandwich effectwith filling layer 430 and dies 420 in between two metal substrates 410and 440.

[0056] Please refer to FIG. 4E, after the adhesion of second metalsubstrate 440, first metal substrate 410 is removed by etching untilreaching insulating 414 and preserving insulating layer 414 on top ofdies 410 and filling layer 430. First metal substrate is used to providea planar surface (surface 412 in FIG. 4A) for the adhesion and formationof insulating layer 414. Therefore first metal substrate can be replacedby substrate of other material such as glass, ceramic, metal, or otherorganic material.

[0057] Please refer to FIG. 4F, after the thinning of first metalsubstrate 410, a plurality of first thru-holes 410 a are formed oninsulating layer 414 for exposing metal pads 426 of active surface 422of die 420. First thru-holes 410 a can be formed by machine drilling,laser, plasma etching, or similar methods.

[0058] Please refer to FIG. 4G, a first patterned wiring layer 450 isformed on insulating layer 414. Using the same method disclosed in thefirst embodiment of the present invention, first vias 410 b in firstthru-holes 410 a are formed by either filling first thru-holes 410 awith part of the conductive material from patterned wiring layer 450 orpre-filling first thru-holes 410 a with a conductive material before theformation of patterned wiring layer 450. A part of patterned wiringlayer 450 will extend to a region outside active surface 422 of die 420.

[0059] Please refer to FIG. 4H, a dielectric layer 462 is formed oninsulating layer 414 and first patterned wiring layer 450. Whereindielectric layer 462 is patterned to form a plurality of secondthru-holes 462 a, which correspond to bonding pad 450 a of patternedwiring layer 450.

[0060] Please refer to FIG. 4I, a second patterned wiring layer 464 isformed on dielectric layer 462. Using the same method as above, secondvias 462 b in second thru-holes 462 a can be formed by either fillingsecond thru-holes 462 a with part of the conductive material frompatterned wiring layer or pre-fill second thru-holes 462 a with aconductive material before the formation of patterned wiring layer 464.Similarly, in order to redistribute metal pads 426 of dies 420 on secondmetal substrate 440, dielectric layer (462 . . . ), second vias (462 a .. . ), and second patterned wiring layer (464 . . . ) can be repeatedlyformed on dies 420 and metal substrate 440. Wherein insulating layer414, first patterned wiring layer 450, dielectric layer 462 . . . , andsecond patterned wiring layer 464 . . . form thin-film circuit layer460. First vias 410 b, first patterned wiring layer 450, second vias 462b . . . , and second patterned wiring layer 464 form the externalcircuitry of thin-film circuit layer 460.

[0061] The structure of the fourth embodiment of the present inventionafter FIG. 41 will follow FIGS. 1G to 1I from the first embodiment ofthe present invention, therefore it will not be repeated.

[0062] The fourth embodiment of the present invention is a metalsubstrate with the active surface of the dies directly adhered to theinsulating layer of the first metal substrate. A filling layer is formedover the dies and the metal substrate followed by a planarization andthinning process. Afterwards, a second metal substrate is adhered to thedie and the filling layer. A plurality of thru-holes filled withconductive material are formed on the insulating layer. Finally, apatterned wiring layer is formed on the insulating layer allowing theexternal circuitry of the thin-film circuit layer to extend to a regionoutside the active surface of the die to help fan out the metal pads ofthe die.

[0063] The advantage of this structure is increased surface stabilityand accuracy because the active surface of the dies are first adhered tothe surface of the first metal substrate. The thickness of the die canbe very small for reducing the overall thickness of the chip packagebecause no machines handling of dies is required.

[0064] The fifth embodiment of the present invention takes the firsthalf of the fabrication process from the fourth embodiment of thepresent invention and combines with the second half of the fabricationprocess from the first embodiment of the present invention. FIGS. 5A to5E are schematic diagrams of the sectional view illustrating thefabrication of the structure.

[0065] Please refer to FIG. 5A, an insulating layer 514 is formed on topof first surface 512 of metal substrate 510. Following, an activesurface 522 of dies 520 is adhered to a first surface 512 of insulatinglayer 514. Wherein the material of insulating 514 includes metal nitrideor metal oxide. In FIG. 5B, a filling layer 530 is formed on top of dies520 and insulating layer 514 covering dies 520.

[0066] In FIG. 5C, a planarization and thinning process of dies 520 andfilling layer 530 is performed to planarize backside 524 of dies 520 andfilling layer 530. In FIG. 5D, a second metal substrate 540 is formed ontop of dies 520 and filling layer 530 so backside 524 of dies 520adheres to second metal substrate 540. By removing filling layer 530,first metal substrate 510, and insulating layer 514, the metal pads onactive surface 522 of dies 520 are exposed, as illustrated in FIG. 5E.

[0067] First metal substrate 510 and is used to supply a planarizedsurface (first surface 512), and will be removed in later stages of thefabrication process. Therefore first metal substrate 510 can be replacedby substrates of other materials such as glass, metal, silicon, metal,or other organic material. Similarly, insulating layer 514 of firstmetal substrate is also removed in later stages of the fabricationprocess. Therefore it is not necessary to form insulating layer 414 ontop of first metal substrate 510 and directly adheres active surface 522of dies 520 to first surface 512 of first metal substrate 510.

[0068] The structure of the fifth embodiment of the present inventionafter FIG. 5E will follow FIGS. 1B to 1I of the first embodiment of thepresent invention, therefore it will not be repeated.

[0069] The fifth embodiment of the present invention is a metalsubstrate with the active surface of the die adhered to the insulatinglayer of the first metal substrate for allowing high surface stabilityand accuracy. As a result, it eliminates the need of machine handling ofthe dies to achieve a very small thickness of the die for reducing theoverall thickness of the chip package.

[0070] Furthermore, please refer to FIG. 6, it illustrates the schematicdiagram of the sectional view of the chip package structure 600 of thepresent invention for a single die 620. Die 620 is placed on metalsubstrate 610, and a thin-film circuit layer 640 is formed on top of die620 and metal substrate 610. External circuitry 642 of thin-film circuitlayer 640 has at least has one patterned wiring layer 642 a and aplurality of vias 642 b. The thickness of the inner traces inside die620 is usually under 1 micron, but because the high amount of tracescollocated together so RC delay is relatively high and the power/groundbus requires a large area. As a result, the area of die 620 is notenough to accommodate the power/ground bus. Therefore the chip packagestructure 600 uses thin-film circuit layer 640 and external circuitry642 with wider, thicker, and longer traces to alleviate the problem.These traces act an interface for transmitting signals for the internalcircuitry of die 620 or the power/ground bus of die 620. This willimprove the performance of die 620.

[0071] Please refer to FIG. 8, it illustrates a magnified view of thesectional view of the chip package structure of the present invention.Active surface 622 of die 620 has a plurality of active devices 628 a,628 b, and an internal circuitry 624. The internal circuitry 624 forms aplurality of metal pads 626 on the surface of die 620. Therefore signalsare transmitted from active devices 628 a to external circuitry 642 viainternal circuitry 624 of die 620, and from external circuitry 642 backto another active device 628 b via internal circuitry 624. The traces ofexternal circuitry 642 are wider, longer, and thicker than that ofinternal circuitry 624 for providing an improved transmission path.

[0072] Please continue to refer to FIG. 6, external circuitry 642further comprises at least one passive device 644 including a capacitor,an inductor, a resistor, a wave-guide, a filter, a micro electronicmechanical sensor (MEMS), or the like. Passive device 644 can be locatedon a single layer of patterned wiring layer 642 a or between two layersof patterned wiring layers 642 a. In FIGS. 9A, 9B, passive device 644can be formed by printing or other method on two bonding points onpatterned wiring layer 642 a when forming thin-film layer 640. In FIG.10A, a comb-shape passive device 644 (such as a comb capacitor) isformed directly on a single patterned wiring layer. In FIG. 10B, passivedevice 644 (such as a capacitor) is formed between two layers ofpatterned wiring layers 642 a with an insulating material 646 inbetween. Wherein the original dielectric layer (not shown) can replaceinsulating material 646. In FIG. 11A, passive device 644 (such as aninductor) is formed by making a single layer of patterned wiring layer642 a into a circular or square (not shown) spiral. In FIG. 11B,column-shape passive device 644 (such as an inductor) is formed by usingtwo layers of patterned wiring layers 642 a and a plurality of vias 642b to surround an insulating material 646 forming a column. In FIG. 11C,circular-shaped passive device 644 (such as an inductor) is formed byusing slanted traces from two layers of patterned wiring layers and aplurality of vias 642 b to surround an insulating material 646 in acircular manner forming a pie. The above structures allow the originalexternally welded passive devices to be integrated into the inside ofthe chip package structure.

[0073]FIG. 6 illustrates a chip package structure 600 for a single die620 but FIG. 7 illustrates a chip package structure 700 for a pluralityof dies. Chip package structure 700 in FIG. 7 differs from chip packagestructure 600 in FIG. 6 by having a die module 720, which comprises atleast one or more die such as die 720 a, 720 b. Die 720 a, 720 b areelectrically connected by the external circuitry of the thin-filmcircuit layer. The function of die 720 a, 720 b can be the same ordifferent and can be integrated together by external circuitry 742 toform a multi-die module (MCM) by packaging same or different dies intoone chip package structure. When multiple dies are packaged into thesame chip package structure, singulation process is performed on thedetermined number of dies.

[0074] Following the above, the present invention provides a chippackaging method by adhering a die to a metal substrate or to aninwardly protruded area of a metal substrate, and forming a thin-filmcircuit layer with bonding pads and points above the die and metalsubstrate. This structure can fan out the metal pads on the die toachieve a thin chip package structure with high pin count.

[0075] Comparing to the BGA or PGA package technique used in the priorart, the chip package of the present invention is performed directly onthe die and the metal substrate for fanning out the metal pads on thedie. It does not require flip chip or wire bonding to connect the die tothe micro-spaced contact points of a package substrate or carrier. Thepresent invention can reduce cost because the package substrate withmicro-spaced contacts is very expensive. Moreover the signaltransmission path of the present invention is reduced to lessen theeffect of signal delay and attenuation, which improves the performanceof the die.

[0076] Furthermore, the present invention adheres the dies directly tothe metal substrate, due to the high heat conductivity of metal,dissipation of the high heat of the dies during operation is effectivelyincreased. Since a good medium for heat dissipation is provided,performance of the dies is improved. Moreover the well-know-in-the-artfabrication technique on metal substrate and low cost of metal lower thecost of fabricating the metal substrates and further reduce the cost ofchip packaging. In the third embodiment of the present invention, themetal substrate with inwardly protruded areas are formed by overlappinga first metal layer with openings formed by punching and a second metallayer together. The openings of the first metal layer are formed bypunching because punching is low-cost and efficient, which can furtherlower the cost of fabrication of the metal substrate for chip packaging.

[0077] Furthermore, the third embodiment of the present inventionprovides an integrated substrate comprises a silicon layer and a heatconducting layer. A plurality of openings can be pre-formed on thesilicon layer by etching so inwardly protruded areas are formed forinlaying the die when the silicon layer overlaps the heat conductinglayer. The heat conducting layer helps to dissipate heat to the outsidefrom the die during operation, which will effectively increaseperformance. Moreover the CTE of the chips and the metal substrate isidentical so life span and durability of the chips after packaging areincreased. The thin-film layer circuit of the present invention is usedto transmit signals between two main active devices inside the die, orused as a power/ground bus, or used to add in passive devices.Furthermore, the chip package structure of the present invention canaccommodate one or more dies with similar or different functions. Theexternal circuitry of the thin-film circuit layer connects the multipledies together and can be used in a MCM package. The chip packagestructure of the present invention adapts the MCM, the externalcircuitry of the thin-film circuit layer, the passive devices of theexternal circuitry to form a package that is “system in package”.

[0078] It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

What is claimed is:
 1. A chip package structure comprising: a metalsubstrate; a die, wherein the die has an active surface, a backside thatis opposite to the active surface, and a plurality of metal pads locatedon the active surface, whereas the backside of the die is adhered to themetal substrate; and a thin-film circuit layer located on top of themetal substrate and the die and has an external circuitry, wherein theexternal circuitry is electrically connected to the metal pads of thedie and extends to a region outside the active surface of the die, theexternal circuitry has a plurality of bonding pads located on a surfacelayer of the thin-film circuit layer and each bonding pad iselectrically connected to the corresponding metal pad of the die.
 2. Thestructure in claim 1, wherein the die has an internal circuitry and aplurality of active devices located on the active surface of the die andthe internal circuitry is electrically connected to the active devices,whereas the internal circuitry forms the metal pads.
 3. The structure inclaim 2, wherein a signal from one of the active devices is transmittedto the external circuitry via the internal circuitry, and from theexternal circuitry back to one of the active devices via the internalcircuitry.
 4. The structure in claim 3, wherein a width, length, andthickness of traces of the external circuitry are greater thancorresponding traces of the internal circuitry.
 5. The structure inclaim 1, wherein the external circuitry further comprising apower/ground bus.
 6. The structure in claim 1, wherein the thin-filmcircuit layer comprising at least a patterned wiring layer and adielectric layer, the dielectric layer is located on top of the metalsubstrate and the die, and the patterned wiring layer is located on topof the dielectric layer, whereas the patterned wiring layer iselectrically connected to the metal pads of the die through thedielectric layer and forms the external circuitry and the bonding padsof the external circuitry.
 7. The structure in claim 6, wherein thedielectric layer has a plurality of thru-holes, and the patterned wiringlayer is electrically connected to the metal pads of the die by thethru-holes.
 8. The structure in claim 6, wherein a via is located insideeach thru-hole, and the patterned wiring layer is electrically connectedto the metal pads of the die by the vias.
 9. The structure in claim 6,wherein the patterned wiring layer and the vias form the externalcircuitry.
 10. The structure of the claim 6, wherein the externalcircuitry further comprising at least one passive device.
 11. Thestructure in claim 6, wherein the passive device is selected from agroup consisting of a resistor, an inductor, a capacitor, a wave-guide,a filter, and a micro electronic mechanical sensor (MEMS).
 12. Thestructure in claim 10, wherein the passive device is formed by a part ofthe patterned wiring layer.
 13. The structure in claim 6, wherein amaterial of the dielectric layer is selected from a group consisting ofpolyimide, benzocyclobutene, porous dielectric material, and stressbuffer material.
 14. The structure in claim 1, wherein the thin-filmcircuit layer comprising a plurality of patterned wiring layers and aplurality of dielectric layers, in which the patterned wiring layers anddielectric layers are alternately formed and the patterned wiring layersare electrically connected to the neighboring patterned wiring layersthrough the dielectric layer, one of the dielectric layers is formedbetween the thin-film circuit layer and the metal substrate, thepatterned wiring layer that is closest to the metal substrate iselectrically connected to the metal pads of the die through thedielectric layer that is closest to the metal substrate, where thepatterned wiring layer that is furthest away from the metal substrateforms the bonding pads.
 15. The structure in claim 14, wherein each ofthe dielectric layers has a plurality of thru-holes, by which each ofthe patterned wiring layer is electrically connected the neighboringpatterned wiring layers, where the patterned wiring layer that isclosest to the metal substrate is electrically connected to the metalpads of the die through the dielectric layer.
 16. The structure in claim15, wherein a via is located in each thru-hole, by which the patternedwiring layers are electrically connected to the neighboring patternedwiring layers, where the patterned wiring layer that is closest to themetal substrate is electrically connected to the metal pads of the dieby the vias.
 17. The structure in claim 16, wherein the patterned wiringlayers and the vias form the external circuitry.
 18. The structure inclaim 14, wherein the external circuitry further comprising a passivedevice.
 19. The structure in claim 18, wherein the passive device isselected from a group consisting of a resistor, an inductor, acapacitor, a wave-guide, a filter, and a micro electronic mechanicalsensor (MEMS).
 20. The structure in claim 18, wherein the passive deviceis formed by a part of the patterned wiring layer.
 21. The structure inclaim 18, wherein a material of the dielectric layer is selected from agroup consisting of polyimide, benzocyclobutene, porous dielectricmaterial, and stress buffer material.
 22. The structure in claim 1,wherein the metal substrate further comprising an inwardly protrudedarea located on a surface of the metal substrate, where the backside ofthe die is adhered to a bottom of the inwardly protruded area.
 23. Thestructure in claim 1, wherein the metal substrate comprising a firstmetal layer and a second metal layer formed overlapping, a surface ofthe metal substrate is a side of the second metal layer that is furtheraway from the first metal layer, the first metal layer has at least oneopening that penetrates through the first metal layer used to form aninwardly protruded area, and the backside of the die is adhered to abottom of the inwardly protruded area.
 24. The structure in claim 23,wherein a thickness of the first metal layer is approximately equal to athickness of the dies.
 25. The structure in claim 1 further comprising afilling layer located between a surface of the metal substrate and thethin-film circuit layer and surrounding the peripheral of the die, and asurface of the filling layer is planar to the active surface of the die.26. The structure in claim 25, wherein a material of the filling layeris selected from a group consisting of epoxy and polymer.
 27. Thestructure in claim 1 further comprising a passivation layer located ontop of the thin-film circuit layer and exposing the bonding pads. 28.The structure in claim 1 further comprising a plurality of bondingpoints located on the bonding pads.
 29. The structure in claim 28,wherein the bonding points are selected from a group consisting ofsolder balls, bumps, and pins.
 30. A chip package structure comprising:a metal substrate; a plurality of dies, wherein each die has an activesurface, a backside that is opposite to the active surface, and aplurality of metal pads located on the active surface, whereas thebackside of each die is adhered to the metal substrate; and a thin-filmcircuit layer located on top of the metal substrate and the die and hasan external circuitry, wherein the external circuitry is electricallyconnected to the metal pads of the die and extends to a region outsidethe active surface of the die, the external circuitry has a plurality ofbonding pads located on a surface layer of the thin-film circuit layerand each bonding pad is electrically connected to the correspondingmetal pad of the die.
 31. The structure in claim 30, wherein the diesperform same functions.
 32. The structure in claim 30, wherein the diesperform different functions.
 33. The structure in claim 30, wherein thedies have an internal circuitry and a plurality of active deviceslocated on the active surface of the die, and the internal circuitry iselectrically connected to the active devices, whereas the internalcircuitry forms the metal pads.
 34. The structure in claim 33, wherein asignal from one of the active devices is transmitted to the externalcircuitry via the internal circuitry, and from the external circuitryback to one of the active devices via the internal circuitry.
 35. Thestructure in claim 34, wherein a width, length, and thickness of tracesof the external circuitry are greater than corresponding traces of theinternal circuitry.
 36. The structure in claim 30, wherein the externalcircuitry further comprising a power/ground bus.
 37. The structure inclaim 30, wherein the thin-film circuit layer comprising at least apatterned wiring layer and a dielectric layer, the dielectric layer islocated on top of the metal substrate and the die, and the patternedwiring layer is located on top of the dielectric layer, whereas thepatterned wiring layer is electrically connected to the metal pads ofthe die through the dielectric layer and forms the external circuitryand the bonding pads of the external circuitry.
 38. The structure inclaim 37, wherein the dielectric layer has a plurality of thru-holes,and the patterned wiring layer is electrically connected to the metalpads of the die by the thru-holes.
 39. The structure in claim 38,wherein a via is located inside each thru-hole, and the patterned wiringlayer is electrically connected to the metal pads of the die by thevias.
 40. The structure in claim 39, wherein the patterned wiring layerand the vias form the external circuitry.
 41. The structure of the claim37, wherein the external circuitry further comprising at least onepassive device.
 42. The structure in claim 41, wherein the passivedevice is selected from a group consisting of a resistor, an inductor, acapacitor, a wave-guide, a filter, and a micro electronic mechanicalsensor (MEMS).
 43. The structure in claim 41, wherein the passive deviceis formed by a part of the patterned wiring layer.
 44. The structure inclaim 37, wherein a material of the dielectric layer is selected from agroup consisting of polyimide, benzocyclobutene, porous dielectricmaterial, and stress buffer material.
 45. The structure in claim 30,wherein the thin-film circuit layer comprising a plurality of patternedwiring layers and a plurality of dielectric layers, in which thepatterned wiring layers and dielectric layers are alternately formed andthe patterned wiring layers are electrically connected to theneighboring patterned wiring layers through the dielectric layer, one ofthe dielectric layers is formed between the thin-film circuit layer andthe metal substrate, the patterned wiring layer that is closest to themetal substrate is electrically connected to the metal pads of the diesthrough the dielectric layer that is closest to the metal substrate,where the patterned wiring layer that is furthest away from the metalsubstrate forms the bonding pads.
 46. The structure in claim 45, whereineach of the dielectric layers has a plurality of thru-holes, by whicheach of the patterned wiring layer is electrically connected theneighboring patterned wiring layers, where the patterned wiring layerthat is closest to the metal substrate is electrically connected to themetal pads of the dies through the dielectric layer.
 47. The structurein claim 46, wherein a via is located in each thru-hole, by which thepatterned wiring layers are electrically connected to the neighboringpatterned wiring layers, where the patterned wiring layer that isclosest to the metal substrate is electrically connected to the metalpads of the die by the vias.
 48. The structure in claim 47, wherein thepatterned wiring layers and the vias form the external circuitry. 49.The structure in claim 45, wherein the external circuitry furthercomprising a passive device.
 50. The structure in claim 49, wherein thepassive device is selected from a group consisting of a resistor, aninductor, a capacitor, a wave-guide, a filter, and a micro electronicmechanical sensor (MEMS).
 51. The structure in claim 49, wherein thepassive device is formed by a part of the patterned wiring layer. 52.The structure in claim 45, wherein a material of the dielectric layer isselected from a group consisting of polyimide, benzocyclobutene, porousdielectric material, and stress buffer material.
 53. The structure inclaim 30, wherein the metal substrate further comprising a plurality ofinwardly protruded areas located on a surface of the metal substrate andthe backside of the dies is adhered to a bottom of the inwardlyprotruded areas.
 54. The structure in claim 30, wherein the metalsubstrate comprising a first metal layer and a second metal layer formedoverlapping, a surface of the metal substrate is a side of the secondmetal layer that is further away from the first metal layer, the firstmetal layer has at least one opening that penetrates through the firstmetal layer used to form the inwardly protruded areas, and the backsideof the die is adhered to a bottom of the inwardly protruded areas. 55.The structure in claim 54, wherein a thickness of the first metal layeris approximately equal to a thickness of the dies.
 56. The structure inclaim 30 further comprising a filling layer located between a surface ofthe metal substrate and the thin-film circuit layer and surrounding theperipheral of the die, and a surface of the filling layer is planar tothe active surface of the die.
 57. The structure in claim 56, wherein amaterial of the filling layer is selected from a group consisting ofepoxy and polymer.
 58. The structure in claim 30 further comprising apassivation layer located on top of the thin-film circuit layer andexposing the bonding pads.
 59. The structure in claim 30 furthercomprising a plurality of bonding points located on the bonding pads.60. The structure in claim 59, wherein the bonding points are selectedfrom a group consisting of solder balls, bumps, and pins.
 61. A chippackaging method comprising: providing a metal substrate with a surface;providing a plurality of dies, wherein each die has an active surface, abackside that is opposite to the active surface, and a plurality ofmetal pads located on the active surface, whereas the backside of eachdie is adhered to the surface of the metal substrate; allocating a firstdielectric layer on top of the surface of the metal substrate and theactive surface of the dies; and allocating a first patterned wiringlayer on top of the first dielectric layer, wherein the first patternedwiring layer is electrically connected to the metal pads of the diesthrough the first dielectric layer, extends to a region outside of anarea above the active surfaces of the dies, and has a plurality of firstbonding pads.
 62. The method of claim 61, wherein the dies perform samefunctions.
 63. The method of claim 61, wherein the dies performdifferent functions.
 64. The method of claim 61, wherein the metalsubstrate has a plurality of inwardly protruded areas located on thesurface of the metal substrate, where the backside of each die isadhered to a bottom of an inwardly protruded area.
 65. The method ofclaim 64, wherein a depth of the inwardly protruded areas is equal to athickness of the dies.
 66. The method of claim 64, wherein the inwardlyprotruded areas are formed by machining.
 67. The method of claim 61,wherein the metal substrate comprising a first metal layer and a secondmetal layer formed overlapping, a surface of the metal substrate is aside of the second metal layer that is further away from the first metallayer, the first metal layer has at least one opening that penetratesthrough the first metal layer used to form an inwardly protruded areas,and the backside of the dies is adhered to a bottom of the inwardlyprotruded areas.
 68. The method of claim 67, wherein a thickness of thefirst metal layer is approximately equal to a thickness of the dies. 69.The method of claim 67, wherein a method of forming openings on thefirst metal layer comprising punching and then overlapping the firstmetal layer and the second metal layer to form the metal substrate. 70.The method of claim 61, wherein after adhering the dies and beforeallocating the first dielectric layer, further comprising allocating afilling layer on top of the surface of the metal substrate andsurrounding the peripheral of the dies, and a top surface of the fillinglayer is planar to the active surface of the dies.
 71. The method ofclaim 70, wherein a material of the filling layer is selected from agroup consisting of epoxy and polymer.
 72. The method of claim 61,wherein after allocating the first dielectric layer and beforeallocating the first patterned wiring layer, further comprisingpatterning the first dielectric layer to form a plurality of firstthru-holes that penetrates through the first dielectric layer, and thefirst patterned conductive is electrically connected to the metal padsof the dies by the first thru-holes.
 73. The method of claim 72, whereinwhen allocating the first patterned wiring layer on the first dielectriclayer, further includes allocating a plurality of first vias by fillingpart of a conductive material of the first patterned conductive layerinto the thru-holes to electrically connect the first patterned wiringlayer and the metal pads of the dies by the first vias.
 74. The methodof claim 72, wherein when allocating the first patterned wiring layer ontop of the first dielectric layer, further comprising filling the firstthru-holes with a conductive material to form a plurality of first vias,by which the first patterned wiring layer and the metal pads areelectrically connected.
 75. The method of claim 61, wherein a materialof the first dielectric layer is selected from a group consisting ofpolyimide, benzocyclobutene, porous dielectric material, and stressbuffer material.
 76. The method of claim 61, wherein the method ofallocating the first patterned wiring layer on top of the firstdielectric layer is selected from a group consisting of sputtering,electroplating, and electro-less plating.
 77. The method of claim 61,further comprising allocating a patterned passivation layer on top ofthe first dielectric layer and the first patterned wiring layer andexposing the first bonding pads.
 78. The method of claim 61, furthercomprising allocating a bonding point on the first bonding pads.
 79. Themethod of claim 78, wherein the bonding points are selected from a groupconsisting of solder balls, bumps, and pins.
 80. The method of claim 78,further comprising singularizing the chip package structure afterallocating the bonding point on the bonding pads.
 81. The method ofclaim 80, wherein a singularization of the chip package structure isperformed on a single die.
 82. The method of claim 80, wherein asingularization of the chip package structure is performed on aplurality of dies.
 83. The method of claim 61 further comprising: (a)allocating a second dielectric layer on top of the first dielectriclayer and the first patterned wiring layer; and (b) allocating a secondpatterned wiring layer on top the second dielectric layer, wherein thesecond patterned wiring layer is electrically connected to the firstpatterned wiring layer through the second dielectric layer, and thesecond patterned wiring layer extends to a region outside the activesurface of the die and has a plurality of second bonding pads.
 84. Themethod of claim 83, wherein after allocating the second dielectric layerand before allocating the second patterned wiring layer, furthercomprising patterning the second dielectric layer to form a plurality ofsecond thru-holes, which corresponds to the first thru-holes andpenetrates the second dielectric layer, to electrically connect to thefirst patterned wiring layer.
 85. The method of claim 84, wherein whenallocating the second patterned wiring layer on top of the seconddielectric layer, further comprising filling the second thru-holes withpart of a conductive material of the second patterned wiring layer toform a plurality of second vias, by which the second patterned wiringlayer is electrically connected to the first patterned wiring layer. 86.The method of claim 84, wherein before allocating the second patternedwiring layer on top of the second dielectric layer, further comprisingfilling the second thru-holes with a conductive material to form aplurality of second vias, by which the second patterned wiring layer iselectrically connected to the first patterned wiring layer.
 87. Themethod of claim 83, wherein a material of the second dielectric layer isselected from a group consisting of polyimide, benzocyclobutene, porousdielectric material, and stress buffer material.
 88. The method of claim83, wherein the method of allocating the second patterned wiring layeron the second dielectric layer is selected from a group consisting ofsputtering, electroplating, and electro-less plating.
 89. The method ofclaim 83, further comprising allocating a patterned passivation layer ontop of the second dielectric layer and the second patterned wiring layerand exposing the second bonding pads.
 90. The method of claim 83,further comprising allocating a bonding point on the second bondingpads.
 91. The method of claim 90, wherein the bonding points areselected from a group consisting of solder balls, bumps, and pins. 92.The method of claim 90, further comprising singularizing the chippackage structure after allocating the bonding point on the secondbonding pads.
 93. The method of claim 92, wherein a singularization ofthe chip package structure is performed on a single die.
 94. The methodof claim 92, wherein a singularization of the chip package structure isperformed on a plurality of dies.
 95. The method of claim 83, furthercomprising repeating step (a) and step (b) a plurality of times.
 96. Themethod of claim 95 further comprising allocating a patterned passivationlayer on the second dielectric layer and the second patterned wiringlayer that is furthest away from the metal substrate and exposing thesecond bonding pads of the second patterned wiring layer that isfurthest away from the metal substrate.
 97. The method of claim 95,further comprising allocating a bonding point on the second bonding padsof the second dielectric layer that is furthest away from the metalsubstrate.
 98. The method of claim 97, wherein the bonding points areselected from a group consisting of solder balls, bumps, and pins. 99.The method of claim 97, further comprising singularizing the chippackage structure after allocating the bonding point on the secondbonding pads.
 100. The method of claim 99, wherein a singularization ofthe chip package structure is performed on a single die.
 101. The methodof claim 100, wherein a singularization of the chip package structure isperformed on a plurality of dies.
 102. A chip packaging methodcomprising: providing a substrate with a first surface; providing aplurality of dies, wherein each die has an active surface, a backsidethat is opposite to the active surface, and a plurality of metal padslocated on the active surface, whereas the active surface of each die isadhered to the first surface of the substrate; allocating a firstfilling layer on top of the first surface of the substrate andsurrounding the dies; planarizing and thinning of the first fillinglayer and the dies; providing a metal substrate with a second surfaceand adhering the second surface of the metal substrate to the firstfilling layer and the dies; removing the first filling layer and thesubstrate; allocating a first dielectric layer on the second surface ofthe metal substrate and the active surface of the dies; and allocating afirst patterned wiring layer on top of the first dielectric layer,wherein the first patterned wiring layer is electrically connected tothe metal pads of the dies through the first dielectric layer, extendsto a region outside the active surfaces of the dies, and has a pluralityof first bonding pads.
 103. The method of claim 102, wherein the diesperform same functions.
 104. The method of claim 102, wherein the diesperform different functions.
 105. The method of claim 102, wherein amaterial of the substrate is selected from a group consisting of glass,silicon, and organic material.
 106. The method of claim 102, wherein amaterial of the first filling layer is selected from a group consistingof epoxy and polymer.
 107. The method of claim 102, wherein afteradhering the metal substrate and before removing the first filling layerand the substrate, further comprising allocating a second filling layeron top of the second surface of the metal substrate, the second fillinglayer surrounds a peripheral of the dies and has a top surface that isplanar to the active surface of the dies.
 108. The method of claim 107,wherein a material of the second filling layer is selected from a groupconsisting of epoxy and polymer.
 109. The method of claim 102, whereinafter allocating the first dielectric layer and before allocating thefirst patterned wiring layer, further comprising patterning the firstdielectric layer to form a plurality of first thru-holes, by which thefirst patterned wiring layer is electrically connected to the metal padsof the dies.
 110. The method of claim 109, wherein when allocating thefirst patterned wiring layer on top of the first dielectric layer,further comprising filling the first thru-holes with part of aconductive material of the first patterned wiring layer to form aplurality of first vias, by which the first patterned wiring layer iselectrically connected to the metal pads of the dies.
 111. The method ofclaim 109, wherein before allocating the first patterned wiring layer ontop of the first dielectric layer, further comprising filling the firstthru-holes with a conductive material to form a plurality of first vias,by which the first patterned wiring layer is electrically connected tothe metal pads of the dies.
 112. The method of claim 102, wherein amaterial of the first dielectric layer is selected from a groupconsisting of polyimide, benzocyclobutene, porous dielectric material,and stress buffer material.
 113. The method of claim 102, wherein amethod of allocating the first patterned wiring layer on the firstdielectric layer is selected from a group consisting of sputtering,electroplating, and electro-less plating.
 114. The method of claim 102,further comprising allocating a patterned passivation layer on top ofthe first dielectric layer and the first patterned wiring layer andexposing the first bonding pads.
 115. The method of claim 102, furthercomprising allocating a bonding point on the first bonding pads. 116.The method of claim 115, wherein the bonding points are selected from agroup consisting of solder balls, bumps, and pins.
 117. The method ofclaim 115, further comprising singularizing the chip package structureafter allocating the bonding point on the first bonding pads.
 118. Themethod of claim 117, wherein a singularization of the chip packagestructure is performed on a single die.
 119. The method of claim 117,wherein a singularization of the chip package structure is performed ona plurality of dies.
 120. The method of claim 102 further comprising:(a) allocating a second dielectric layer on top of the first dielectriclayer and the first patterned wiring layer; and (b) allocating a secondpatterned wiring layer on top the second dielectric layer, wherein thesecond patterned wiring layer is electrically connected to the firstpatterned wiring layer through the second dielectric layer, and thesecond patterned wiring layer extends to a region outside the activesurface of the die and has a plurality of second bonding pads.
 121. Themethod of claim 120, wherein after allocating the second dielectriclayer and before allocating the second patterned wiring layer, furthercomprising patterning the second dielectric layer to form a plurality ofsecond thru-holes, which corresponds to the first bonding pads andpenetrates the second dielectric layer, to electrically connect to thefirst patterned wiring layer.
 122. The method of claim 121, wherein whenallocating the second patterned wiring layer on top of the seconddielectric layer, further comprising filling the second thru-holes withpart of a conductive material of the second patterned wiring layer toform a plurality of second vias, by which the second patterned wiringlayer is electrically connected to the first patterned wiring layer.123. The method of claim 121, wherein before allocating the secondpatterned wiring layer on top of the second dielectric layer, furthercomprising filling the second thru-holes with a conductive material toform a plurality of second vias, by which the second patterned wiringlayer is electrically connected to the first patterned wiring layer.124. The method of claim 120, wherein a material of the seconddielectric layer is selected from a group consisting of polyimide,benzocyclobutene, porous dielectric material, and stress buffermaterial.
 125. The method of claim 120, wherein a method of allocatingthe second patterned wiring layer on the second dielectric layer isselected from a group consisting of sputtering, electroplating, andelectro-less plating.
 126. The method of claim 120, further comprisingallocating a patterned passivation layer on top of the second dielectriclayer and the second patterned wiring layer and exposing the secondbonding pads.
 127. The method of claim 120, further comprisingallocating a bonding point on the second bonding pads.
 128. The methodof claim 127, wherein the bonding points are selected from a groupconsisting of solder balls, bumps, and pins.
 129. The method of claim127, further comprising singularizing the chip package structure afterallocating the bonding point on the second bonding pads.
 130. The methodof claim 129, wherein a singularization of the chip package structure isperformed on a single die.
 131. The method of claim 129, wherein asingularization of the chip package structure is performed on aplurality of dies.
 132. The method of claim 120, further comprisingrepeating step (a) and step (b) a plurality of times.
 133. The method ofclaim 132 further comprising allocating a patterned passivation layer onthe second dielectric layer and the second patterned wiring layer thatare furthest away from the metal substrate and exposing the secondbonding pads of the second patterned wiring layer that is furthest awayfrom the metal substrate.
 134. The method of claim 132, furthercomprising allocating a bonding point on the second bonding pads of thesecond patterned wiring layer that is furthest away from the metalsubstrate.
 135. The method of claim 134, wherein the bonding points areselected from a group consisting of solder balls, bumps, and pins. 136.The method of claim 134, further comprising singularizing the chippackage structure after allocating the bonding point on the secondbonding pads.
 137. The method of claim 136, wherein a singularization ofthe chip package structure is performed on a single die.
 138. The methodof claim 136, wherein a singularization of the chip package structure isperformed on a plurality of dies.